This invention relates to a data transfer control system and more particularly to a system for controlling the use of a common data transfer bus shared by a plurality of data processors.
With a complex system comprising a plurality of microcomputers or minicomputers, one common data transfer bus or shared-memory is shared by a plurality of data processors (abbreviated as "CPU"). For example, with a multiprocessor system, control of the priority use of the common bus should be efficiently carried out according to the sequential priority position of the selected one of said CPU's for said use.
To date, the use of a common bus has been controlled by receiving signals from the respective CPU's demanding the use of the common bus in the order of earlier arrivals or previously allotting a fixed priority to signals from the respective CPU's demanding the use of the common bus by means of hardware structure and receiving the common bus use-demanding signals according to the fixed sequential order of said allotted priorities. Once a selected CPU is allowed to use the common bus, the other CPU's are held in a waiting position, until the use of the common bus by said selected CPU is brought to an end.
One of the prior art common bus use-controlling systems, that is, the receipt of signals demanding the priority use of the common bus in the order of earlier arrivals, has the drawback that since no priority is taken into consideration with respect to these signals, a sudden important or urgent demand for the use of the common bus can not be successfully met. On the other hand, where the priority of using the common bus is fixedly allotted to the respective CPU's by means of hardware structure, then the following drawbacks arise. Namely, it is impossible to enable the whole multiprocessor system to admit of quick adjustment for changes in the priority order of signals demanding the use of the common bus caused by the variation of the type of processing job or the changing of processing jobs from one to another in said multiprocessor system. Further, where a specified CPU is allowed to use the common bus, for example, continuously for long hours, then the other CPU's are kept in a waiting position, until the use of the common bus by said specified CPU is brought to an end. Therefore, any of said other CPU's which happens urgently to demand the use of the common bus still have to be kept waiting long.